IRQ assignments

IRQ pins configuration is the part of generic constants defined in file ambalib/types_amba4.vhd. Number of interrupts and its indexes can changed in future releases.

Pin	Name	Description
0	Unused	Zero Interrupt pin is unsued and connected to Ground.
1	UART1	Uart 1 IRQ. UART device used this line to signal CPU via Interrupt Controller that new data is available or device ready to accept new Rx data.
2	ETHMAC	Ethernet IRQ.
3	GPTIMERS	General Purpose Timers IRQ.
4	MISS_ACCESS	Memory Miss Access IRQ. This interrupt is generated by AXI Controller in a case of access to unmapped memory region.
5	GNSSENGINE	Gnss Engine IRQ. Device Specific 1 msec interrupt that schedules critical Navigation Task.

IRQ Controller registers mapping

IRQ Controller acts like a slave AMBA AXI4 device that is directly mapped into physical memory. Default address location for our implementation is defined by 0x80002000. Memory size is 4 KB.

Interrupts Mask register (0x000).

Bits	Type	Reset	Field Name	Bits	Description
32-N	RW	h'0	reserved	31:N	Reserved
N	RW	all 1	mask	N-1:0	IRQ mask. 1 equals interrupt disabled; 0 is enabled.

Pending Interrupts register (0x004).

Bits	Type	Reset	Field Name	Bits	Description
32-N	RO	h'0	reserved	31:N	Reserved
N	RO	0	pending	N-1:0	Pending Bits. 1 signals rised interrupt. This bit is cleared by writing 1 into the register 'Clear IRQ' or writing 1 into 'Lock Register'.

Clear Interrupt Mask register (0x008).

Bits	Type	Reset	Field Name	Bits	Description
32-N	WO	h'0	reserved	31:N	Reserved
N	WO	0	clear_bit	N-1:0	Clear IRQ line. Clear Pending interrupt register bits that are marked with 1s.

Raise Interrupt Mask register (0x00C).

Bits	Type	Reset	Field Name	Bits	Description
32-N	WO	h'0	reserved	31:N	Reserved
N	WO	0	raise_irq	N-1:0	Rise specified IRQ line manually. This register can be used for test and debugging either as for 'system calls'.

ISR table address (low word) (0x010).

Bits	Type	Reset	Field Name	Bits	Description
32	WR	0	isr_table	31:0	Interrupts table address LSB. This register stores address where located ISR table. This value must be intialized be Software.

ISR table address (high word) (0x014).

Bits	Type	Reset	Field Name	Bits	Description
32	WR	0	isr_table	31:0	Interrupts table address MSB. This register stores address where located ISR table. This value must be intialized be Software.

ISR cause code (low word) (0x018).

Bits	Type	Reset	Field Name	Bits	Description
32	WR	0	dbg_cause	31:0	Cause of te Interrupt LSB. This register stores the latest cause of the interrupt. This value is optional and updates by ROM ISR handler in current implementation.

ISR cause code (high word) (0x01C).

Bits	Type	Reset	Field Name	Bits	Description
32	WR	0	dbg_cause	31:0	Cause of the Interrupt MSB. This register stores the latest cause of the interrupt. This value is optional and updates by ROM ISR handler in current implementation.

Instruction Pointer before trap (low word) (0x020).

Bits	Type	Reset	Field Name	Bits	Description
32	WR	0	dbg_epc	31:0	npc[31:0] register value before trap . This register stores copy of xEPC value. This value is optional and updates by ROM ISR handler in current implementation.

Instruction Pointer before trap (high word) (0x024).

Bits	Type	Reset	Field Name	Bits	Description
32	WR	0	dbg_epc	31:0	npc[63:32] register value before trap. This register stores copy of xEPC value. This value is optional and updates by ROM ISR handler in current implementation.

Lock interrupt register (0x028).

Bits	Type	Reset	Field Name	Bits	Description
31	WR	31h'0	reserved	31:1	Reserved
1	WR	1b'	lock	0	Lock interrupts. Disabled all interrupts when this bit is 1. All new interrupt request marked as postponed and will be raised when 'lock' signal will be cleared.

Lock interrupt register (0x02C).

Bits	Type	Reset	Field Name	Bits	Description
32	WR	0	irq_idx	31:0	Interrupt Index. This register stores current interrupt index while in ISR handler. This value is optional and updates by ROM ISR handler in current implementation.