RISC-V VHDL: System-on-Chip  2.0
RTL Verification

Top-level simulation

Test-bench example
Use file work/tb/riscv_soc_tb.vhd to run simulation scenario. You can get the following time diagram after simulation of 2 ms interval.
Simulating top
Note
Simulation behaviour depends of current firmware image. It may significantly differs in a new releases either as Zephyr OS kernel image is absolutely different relative GNSS FW image.

Some FW versions can detect RTL simulation target by reading 'Target' Register in PnP device that allows to speed-up simulation by removing some delays and changing Devices IO parameters (UART speed for example).

Running on FPGA
Supported FPGA:
  • ML605 with Virtex6 FPGA using ISE 14.7 (default).
  • KC705 with Kintex7 FPGA using Vivado 2015.4.
Warning
In a case of using GNSS FW without connected RF front-end don't forget to switch ON DIP[0] (i_int_clkrf) to enable Test Mode. Otherwise there wouldn't be generated interrupts and, as result, no UART output.

VCD-files automatic comparision

Generating VCD-pattern form SystemC model

Edit the following attributes in SystemC target script debugger/targets/sysc_river_gui.json to enable vcd-file generation.

  • ['InVcdFile','i_river','Non empty string enables generation of stimulus VCD file'].
  • ['OutVcdFile','o_river','Non empty string enables VCD file with reference signals']

Files i_river.vcd and o_river.vcd will be generated. The first one will be used as a RTL simulation stimulus to generate input signals. The second one as a reference.

Compare RIVER SystemC model relative RTL

Run simulation in ModelSim with the following commands using correct pathes for your host: 

 vcd2wlf E:/Projects/GitProjects/riscv_vhdl/debugger/win32build/Debug/i_river.vcd -o e:/i_river.wlf
 vcd2wlf E:/Projects/GitProjects/riscv_vhdl/debugger/win32build/Debug/o_river.vcd -o e:/o_river.wlf
 wlf2vcd e:/i_river.wlf -o e:/i_river.vcd
 vsim -t 1ps -vcdstim E:/i_river.vcd riverlib.RiverTop
 vsim -view e:/o_river.wlf
 add wave o_river:/SystemC/o_*
 add wave sim:/rivertop/*
 run 500us
 compare start o_river sim
 compare add -wave sim:/RiverTop/o_req_mem_valid o_river:/SystemC/o_req_mem_valid
 compare add -wave sim:/RiverTop/o_req_mem_write o_river:/SystemC/o_req_mem_write
 compare add -wave sim:/RiverTop/o_req_mem_addr o_river:/SystemC/o_req_mem_addr
 compare add -wave sim:/RiverTop/o_req_mem_strob o_river:/SystemC/o_req_mem_strob
 compare add -wave sim:/RiverTop/o_req_mem_data o_river:/SystemC/o_req_mem_data
 compare add -wave sim:/RiverTop/o_dport_ready o_river:/SystemC/o_dport_ready
 compare add -wave sim:/RiverTop/o_dport_rdata o_river:/SystemC/o_dport_rdata
 compare run
Note
In this script I've used vcd2wlf and wlf2vcd utilities to form compatible with ModelSim VCD-file. Otherwise there're will be errors because ModelSim cannot parse std_logic_vector siganls (only std_logic).