SoC configuration constants

Entities
config_common	package
	Techology independent configuration settings. More...

Libraries
techmap
	Technology definition library.

Use Clauses
gencomp
	Generic IDs constants import.

Constants
CFG_COMMON_RIVER_CPU_ENABLE	boolean := true
	Disable/Enable River CPU instance.
CFG_SIM_BOOTROM_HEX	string := " ../../fw_images/bootimage.hex "
	HEX-image for the initialization of the Boot ROM.
CFG_SIM_FWIMAGE_HEX	string := " ../../fw_images/fwimage.hex "
	HEX-image for the initialization of the FwImage ROM.
CFG_GNSSLIB_ENABLE	boolean := false
	Disable/Enable usage of the gnsslib library.
CFG_GNSSLIB_GNSSENGINE_ENABLE	boolean := false
	Enable GNSS Engine module.
CFG_GNSSLIB_FSEGPS_ENABLE	boolean := false
	Enable Fast Search Engine for the GPS signals.
CFG_ETHERNET_ENABLE	boolean := true
	Enabling Ethernet MAC interface.
CFG_DSU_ENABLE	boolean := true
	Enable/Disable Debug Unit.
CFG_TESTMODE_ON	boolean := true
	Remove BUFGMUX from project and use internaly generate ADC clock.

Detailed Description

Target independible constants that are the same for FPGA, ASIC and behaviour simulation.

Variable Documentation

CFG_COMMON_RIVER_CPU_ENABLE

CFG_COMMON_RIVER_CPU_ENABLE boolean := true

Constant

Disable/Enable River CPU instance.

When enabled platform will instantiate processor named as "RIVER" entirely written on VHDL. Otherwise "Rocket" will be used (developed by Berkley team).

Warning

DSU available only for "RIVER" processor.

CFG_ETHERNET_ENABLE

CFG_ETHERNET_ENABLE boolean := true

Constant

Enabling Ethernet MAC interface.

By default MAC module enables support of the debug feature EDCL.

CFG_GNSSLIB_ENABLE

CFG_GNSSLIB_ENABLE boolean := false

Constant

Disable/Enable usage of the gnsslib library.

This 'gnsslib' is the property of the "GNSS Sensor ltd" (www.gnss-sensor.com) and it implements a lot of Navigation related peripheries, like:

• RF front-end synthezators controller;
• Multi-system GNSS Engine;
• Fast Search modules;
• Viterbi decoders;
• Self-test generators and so on.

Warning

This define enables RF front-end clock as a source of ADC clock.

CFG_SIM_BOOTROM_HEX

CFG_SIM_BOOTROM_HEX string := " ../../fw_images/bootimage.hex "

Constant

HEX-image for the initialization of the Boot ROM.

This file is used by inferred ROM implementation.

CFG_SIM_FWIMAGE_HEX

CFG_SIM_FWIMAGE_HEX string := " ../../fw_images/fwimage.hex "

Constant

HEX-image for the initialization of the FwImage ROM.

This file is used by inferred ROM implementation.

CFG_TESTMODE_ON

CFG_TESTMODE_ON boolean := true

Constant

Remove BUFGMUX from project and use internaly generate ADC clock.

We have some difficulties with Vivado + Kintex7 constrains, so to make test-mode stable working we use this temporary config parameter that hardcodes 'test_mode' is always enabled